The present invention is generally directed to data processors and, more specifically, to a memory-mapped cache flushing device for use in a data processor.
The demand for high performance computers requires that state-of-the-art microprocessors execute instructions in the minimum amount of time. A number of different approaches have been taken to decrease instruction execution time, thereby increasing processor throughput. One way to increase processor throughput is to use a pipeline architecture in which the processor is divided into separate processing stages that form the pipeline. Instructions are broken down into elemental steps that are executed in different stages in an assembly line fashion.
A pipelined processor is capable of executing several different machine instructions concurrently. This is accomplished by breaking down the processing steps for each instruction into several discrete processing phases, each of which is executed by a separate pipeline stage. Hence, each instruction must pass sequentially through each pipeline stage in order to complete its execution. In general, a given instruction is processed by only one pipeline stage at a time, with one clock cycle being required for each stage. Since instructions use the pipeline stages in the same order and typically only stay in each stage for a single clock cycle, an N stage pipeline is capable of simultaneously processing N instructions. When filled with instructions, a processor with N pipeline stages completes one instruction each clock cycle.
The execution rate of an N-stage pipeline processor is theoretically N times faster than an equivalent non-pipelined processor. A non-pipelined processor is a processor that completes execution of one instruction before proceeding to the next instruction. Typically, pipeline overheads and other factors decrease somewhat the execution rate advantage that a pipelined processor has over a non-pipelined processor.
An exemplary seven stage processor pipeline may consist of an address generation stage, an instruction fetch stage, a decode stage, a read stage, a pair of execution (E1 and E2) stages, and a write (or write-back) stage. In addition, the processor may have an instruction cache that stores program instructions for execution, a data cache that temporarily stores data operands that otherwise are stored in processor memory, and a register file that also temporarily stores data operands.
The address generation stage generates the address of the next instruction to be fetched from the instruction cache. The instruction fetch stage fetches an instruction for execution from the instruction cache and stores the fetched instruction in an instruction buffer. The decode stage takes the instruction from the instruction buffer and decodes the instruction into a set of signals that can be directly used for executing subsequent pipeline stages. The read stage fetches required operands from the data cache or registers in the register file. The E1 and E2 stages perform the actual program operation (e.g., add, multiply, divide, and the like) on the operands fetched by the read stage and generates the result. The write stage then writes the result generated by the E1 and E2 stages back into the data cache or the register file.
Assuming that each pipeline stage completes its operation in one clock cycle, the exemplary six stage processor pipeline takes six clock cycles to process one instruction. As previously described, once the pipeline is full, an instruction can theoretically be completed every clock cycle.
The throughput of a processor also is affected by the size of the instruction set executed by the processor and the resulting complexity of the instruction decoder. Large instruction sets require large, complex decoders in order to maintain a high processor throughput. However, large complex decoders tend to increase power dissipation, die size and the cost of the processor. The throughput of a processor also may be affected by other factors, such as exception handling, data and instruction cache sizes, multiple parallel instruction pipelines, and the like. All of these factors increase or at least maintain processor throughput by means of complex and/or redundant circuitry that simultaneously increases power dissipation, die size and cost.
In many processor applications, the increased cost, increased power dissipation, and increased die size are tolerable, such as in personal computers and network servers that use x86-based processors. These types of processors include, for example, Intel Pentium(trademark) processors and AMD Athlon(trademark) processors.
However, in many applications it is essential to minimize the size, cost, and power requirements of a data processor. This has led to the development of processors that are optimized to meet particular size, cost and/or power limits. For example, the recently developed Transmeta Crusoe(trademark) processor greatly reduces the amount of power consumed by the processor when executing most x86 based programs. This is particularly useful in laptop computer applications. Other types of data processors may be optimized for use in consumer appliances (e.g., televisions, video players, radios, digital music players, and the like) and office equipment (e.g., printers, copiers, fax machines, telephone systems, and other peripheral devices). The general design objectives for data processors used in consumer appliances and office equipment are the minimization of cost and complexity of the data processor.
One important function that can impact the size, complexity, cost and throughput of a data processor is the cache flushing operation. Cache flushes occur whenever the processor wants to invalidate data in the cache. Depending on the processor architecture, a cache flush may occur for the entire cache or for one or more selected lines in the cache.
Conventional data processors implement a number of different schemes for performing cache flushes. Some processors implement operations in the instruction set architecture (ISA) that execute instruction cache and data cache flush operations on a line-by-line basis or on an address basis. The disadvantage to this technique is that a cache flush is a complex operation to support and in some areas (e.g., embedded processors), it is desirable to avoid adding this overhead to the ISA.
Some processors implement a simpler cache flush operation that flushes all of the data or instruction cache. While this technique may be less complex to implement, it has the disadvantage that the granularity of the flush is the entire cache and it is not possible to individually flush single cache lines. Still other processors rely entirely on software to perform a cache flush. Software can achieve the same effect as a cache flush operation by traversing a properly designed area of memory (code or data) containing no useful values and by making sure that all the interested locations of the cache are touched by the traversal. This technique has the disadvantage that an amount of physical memory equal to the cache size has to be permanently allocated to store the proper values. In some areas where memory is limited (e.g., embedded processor systems), this type of solution is unacceptable.
Therefore, there is a need in the art for data processors that implement simple, adaptable circuitry to perform cache flushes. In particular, there is a need in the art for a data processor that is capable of performing cache flushes on a line-by-line basis without modifying the instruction set architecture to implement complex decode circuitry. More particularly, there is a need in the art for a data processor that is capable of performing cache flush operations on a line-by line basis without permanently allocating a portion of physical memory equal to the cache size to store the proper values.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a data processor that includes an instruction execution pipeline having N processing stages and a memory cache including a plurality of storage lines at which data is storable. A cache flush apparatus is coupled to permit access thereof to storage lines of the memory cache of the instruction execution pipeline. The cache flush apparatus is selectably operable to purge at least a selected portion of the memory cache of the instruction execution pipeline. It is a further object of the present invention to provide a method of flushing a data cache associated with a data processor. At least a portion of the data cache is selected at which to flush existing values cached thereat. Selected, arbitrary values are generated at a location separate from the data cache. And, the selected arbitrary values are written to the at least the portion of the data cache, thereby flushing the existing values cached at the selected portion of the data cache.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean is inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.